EDN

Delay- and phase-locked loops becoming reusable IP

San Mateo, Calif. – Phase-locked and delay-locked loops are becoming increasingly important weapons in the system-on-chip design arsenal, but PLLs and DLLs are notorious for their difficulty. Now, ...
Ars Technica

Delay Locked Loop command and some scary binary.

I figured this was the best place to post up about this as it is about settings GDDR3 mode register commands.<br><br>So, The card I have is a 7600GT. Let me go through what exactly i have ...
Design-Reuse

True Circuits Introduces Delay-Locked Loop Hard Macros

Silicon Proven Low-Jitter DLLs Target High-Speed DDR Style Interface Applications LOS ALTOS, California, October 8, 2003 - True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal ...
EDN

Frequency and phase locked loops

The purpose of a phase locked loop (PLL) is to generate a frequency and phase-locked output oscillation signal. To achieve this goal, prior art essentially functioned ...
GPS World

Expert Advice: Quasi-Coherent Delay Lock Loop Tracking and Generalized Binary Coded Symbols in Multipath

The original GPS signals, and indeed most GPS signals including L5, utilize conventional pseudonoise (PN) signal code division multiple access (CDMA), some with both in-phase and quadrature-phase ...